You should set the subdev spec to be "A:0 B:0" and also set "Num Channels" to 2" This will create two ports on the UHD Sink block.
Also you're running GR 3.8 with UHD 3.15. There is a known issue on the UHD Source block (for RX) when operated with 2 channels on GR 3.8 (issue 2612). This may be an issue as well for the Sink block, but I have not tested it yet. If you run into an issue after setting up the subdev and channels, you may want to revert back to GR maint-3.7 branch and use UHD 3.14.1.0 for now, as they are the stable releases.
Regards,
Nate Temple
_______________________________________________We are trying to configure the USRP x300, and we can't get any signal coming out. In the end, we would like to set up this SDR to be a dual channel transmitter to transmit signal on two different frequencies. I will post some diagnostic info here. If anyone could tell me how to configure the device in GNU, I would greatly appreciate it. Thank you.
labuser@THORE0001:~$ sudo uhd_usrp_probe
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501; UHD_3.15.0.git-16-gcad30dfe
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 1472 bytes.
[INFO] [X300] Radio 1x clock: 200 MHz
[INFO] [GPS] No GPSDO found
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D00000000000)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1311 MB/s)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1311 MB/s)
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD100000000001)
[INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD100000000001)
[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0000000000000)
[INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0000000000000)
[INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0000000000000)
[INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0000000000000)
_____________________________________________________
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X300
| | revision: 11
| | revision_compat: 7
| | product: 30817
| | mac-addr0: 00:80:2f:26:60:69
| | mac-addr1: 00:80:2f:26:60:6a
| | gateway: 192.168.10.1
| | ip-addr0: 192.168.10.2
| | subnet0: 255.255.255.0
| | ip-addr1: 192.168.20.2
| | subnet1: 255.255.255.0
| | ip-addr2: 192.168.30.2
| | subnet2: 255.255.255.0
| | ip-addr3: 192.168.40.2
| | subnet3: 255.255.255.0
| | serial: 319CEC8
| | FW Version: 6.0
| | FPGA Version: 36.0
| | FPGA git hash: 4bc2c6f
| | RFNoC capable: Yes
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | ID: UBX-160 v2 (0x007e)
| | | Serial: 31935ED
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: UBX RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | RX Dboard: B
| | | ID: UBX-160 v2 (0x007e)
| | | Serial: 3193632
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: UBX RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: B
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | ID: UBX-160 v2 (0x007d)
| | | Serial: 31935ED
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: UBX TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | TX Dboard: B
| | | ID: UBX-160 v2 (0x007d)
| | | Serial: 3193632
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: UBX TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: B
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | RFNoC blocks on this device:
| | |
| | | * DmaFIFO_0
| | | * Radio_0
| | | * Radio_1
| | | * DDC_0
| | | * DDC_1
| | | * DUC_0
| | | * DUC_1
labuser@THORE0001:~$ sudo uhd_find_devices
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501; UHD_3.15.0.git-16-gcad30dfe
--------------------------------------------------
-- UHD Device 0
--------------------------------------------------
Device Address:
serial: 31764E1
name: L2
product: B205mini
type: b200
--------------------------------------------------
-- UHD Device 1
--------------------------------------------------
Device Address:
serial: 31764E9
name: L1
product: B205mini
type: b200
--------------------------------------------------
-- UHD Device 2
--------------------------------------------------
Device Address:
serial: 319CEC8
addr: 192.168.10.2
fpga: HG
name:
product: X300
type: x300
Paul Mitchell
Engineering Technician IV
256.716.9056 (Work)
256.289.3581 (Cell)
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