thank you for your helpful answer!
In the link you sent, they mention that Q16 Format is used as otw Format.
Is that the same as the signed Q1.15 Format? I think it has to be, because
otherwise only positive numbers could be mapped.
I now managed to add numbers from my registers to my signal in GRC in this
Q1.15 Format by multiplying the values in the registers by 2^15 and round
it to the nearest integer in the xml file at:
yourootmodule/rfnoc/blocks/
Thus, if you write 0.1 to the register, for example with a qt-gui range
block, it gets converted to the 2s complement Q1.15 Format. Maybe that
helps other people too.
Best regards
Felix
> Hi Felix,
>
> The USRPs use signed complex 16 bit integers internally in the FPGA.
> These are converted (optionally!) to signed compled 32 bit floating
> point numbers on the host pc by UHD. The format actually sent over
> USB/Ethernet is called the Over The Wire format and the format that the
> user code facing is the CPU format.
> https://files.ettus.com/manual/structuhd_1_1stream__args__t.html
>
> These conversions are scaling operations, multiplication. Which is why
> your multiplication on the FPGA works as you expect it to. Addition on
> the FPGA must be scaled as you found, using the know ledge that a 16 bit
> signed integer will be converted to/from a floating point number and
> normalized to +-1.
>
> You can set the number formats in the USRP Source and Sink blocks, I
> forget if the RFNoC blocks also support that in GNU Radio Companion, but
> you can certainly do it in the underlying Python and C++.
>
> Cheers,
> Derek
>
> On 13/08/2019 14:12, Felix Greiwe wrote:
>> Hello together,
>>
>> I recently created some RFNoC-Blocks using the RFNoC Modtool and an USRP
>> x310 from ETTUS for future GRC application. My Simulation in Vivado went
>> well and thus I built an FPGA-Image and flashed it to my USRP x310
>> device.
>> In GRC however, I witnessed very strange behaviour considering addition
>> operations of my blocks, so I went back to the most simple functioning
>> block, the RFnOC gain block from the RFNoC getting started page:
>>
>> https://kb.ettus.com/Getting_Started_with_RFNoC_Development
>> (All Source Files are linked at the bottom of that page, no need to read
>> anything to understand my problem)
>>
>> What that block does, is to receive a signal from GNURadio, split it
>> into
>> I and Q Phase and multiply it by a constant value inside the FPGA of the
>> USRP. The outgoing signal is then the product of input and constant, for
>> example 0.1*5 = 0.5. Important in this case is, that the range of
>> result_values are limited to [-1,1] by the fpga.
>>
>> To test addition instead of multiplication (which works), i edited one
>> single line of the noc_block_gain.v file from
>>
>> >> wire [31:0] i_mult_gain = i*gain;
>> >> wire [31:0] q_mult_gain = q*gain;
>>
>> to
>>
>> >> wire [31:0] i_mult_gain = i+gain; // in_phase component (real)
>> >> wire [31:0] q_mult_gain = q*gain; // quadrature phase (imag)
>>
>> where gain is a 16 Bit register which can be adressed through GNURadio
>> Companion.
>>
>> In GRC I created a simple flowgraph which generates a complex cosine
>> with
>> I and Q data samples, which then are prossessed by my modified gain
>> block.
>> I expected the Q-Phase to behave exactly like before, and get multiplied
>> by the value in the gain register, and the I-Data to move upwoards in my
>> GRC Time Sink by the value I add to it.
>>
>> Link to picture of Flowgraph:
>> https://ibb.co/s2jSZtK
>>
>> While the expectations considering the multiplication got fulfilled, in
>> the addition part I see no changes in my results. Only when i pump my
>> gain
>> up to great numbers (for example 10000), i see a shift upwoards in my
>> diagram. My final observation was, that the shift upwoards is close or
>> equal to: "gain_value"/(2^15 -1).
>>
>> Results with "gain" of 5:
>> https://ibb.co/7zJq2zx
>>
>> Results with "gain" of 26214 (~ (2^15 -1)*0.8):
>> https://ibb.co/dtD6cJ7 (Put Q-Data to invisible here, to see I-Data
>> better)
>>
>> At this point I have a few questions, I hope someone can answer:
>>
>> - Why do the operations "multiplication" and "addition" differ in
>> behaviour and how can I get my desired "normal" behaviour?
>>
>> - At which point does GNURadio/RFNoC/theFPGA convert my signals to the
>> range of [-1,1]? Is it always doing this with a fixed formula or only
>> when the number exceeds the range? Any other information considering
>> this?
>>
>> - Does it interpret my 16 Bit gain vector as a simple integer in the
>> multiplication path and as something different,(maybe Q-Format) in the
>> addition path? Why does it not simply add the value of my register to my
>> signal?
>>
>> Any help is greatly appreciated, even when only parts get answered or
>> when
>> it addresses errors in my thougthprocess. I did my best to point out my
>> problem, feel free to ask if you did not understand everything or my
>> mediocre english is an obstacle here.
>>
>> Best regards and thank you reading,
>>
>> Felix Greiwe
>>
>>
>>
>>
>>
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>
>
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