[Discuss-gnuradio] [GSoC19] Weekly report of Verilog simulation phase 3 week 1

Hi all,

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You can find my weekly report here(https://b0wen-hu.github.io/2019/08/04/GSoC-weekly-report-P3W1/).​

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The following content is the abstract  of report, please find the full report at the link above.​

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##Progress this week

I am constructing some converter blocks this week, which make it easir to interact with Verilog modules of different data widths.

I built the Double.v and Sync_fifo.v to test the general-axi block. But I think it still need some more complicated Verilog modules to make sure it works well.

I am working on the error handling part this week as well.

##Plan next week

I think I can use Chisel, a higher level HDL(Hardware Description Language), to build some more complicated module to test the block.

Issue(s)

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Best regards,​

Bowen​