Re: [Discuss-gnuradio] B210 RX bandwidth setting from gnuradio-companion ?

On 04/18/2019 02:14 PM, jmfriedt wrote:
> I am characterizing a weak (-80..-60 dBm) signal next (5 MHz away) to a
> strong (-30..-40 dBm) carrier interfering with my measurement. I am
> looking at power and phase (these are CW signals), and hit the issue
> that the interfering carrier affects the sideband power measurement.
>
> To demonstrate the effect, I mix a 295 MHz +7 dBm LO input (-45 dBm
> output from the mixer isolation) with a -64 dBm RF intput at 5 MHz,
> creating a strong carrier at 295 MHz and a weak sideband at 300 MHz
> with -70 dBm power (due to mixer conversion efficiency of -6 dB).
>
> As mentioned at https://files.ettus.com/manual/page_usrp_b200.html
>
> ---
> The analog frontend has a seamlessly adjustable bandwidth of 200 kHz to
> 56 MHz.
>
> Generally, when requesting any possible master clock rate, UHD will
> automatically configure the analog filters to avoid any aliasing (RX)
> or out-of-band emissions whilst letting through the cleanest possible
> signal.
>
> If you, however, happen to have a very strong interferer within half
> the master clock rate of your RX LO frequency, you might want to reduce
> this analog bandwidth. You can do so by calling
> uhd::usrp::multi_usrp::set_rx_bandwidth(bw).
> ---
>
> so obviously I'd like to reduce RX bandwidth to reject the interfering
> carrier. The question is: how do I do that from the UHD USRP block in
> gnuradio-companion. Since the RX bandwidth in the RF settings seem to
> have no impact on the B210 RX characteristics (I tried a RX bandwidth
> of 200 kHz with no effect on the impact of the carrier 5-MHz away), I
> did follow https://files.ettus.com/manual/page_configuration.html
> and set master_clock_rate=5.12 MHz (my sampling rate is 512 kS/s) which
> indeed allows me to reject the interfering carrier (further away than
> 5.12/2=2.56 MHz) and get a clean phase and power measurement on the
> sideband whatever the carrier power.
>
> Questions:
> 1/ what is the impact of master_clock_rate, i.e. what parameter am I
> modifying by doing this ? The experiment is a physics experiment (ie
> digital lock-in amplifier) and not digital communication, so I do not
> care about bandwidth but I'd like to understand the impact of this
> master_clock_rate.
It's the rate that data are clocked between the AD9361 RFFE chip, and
the FPGA.

I'm not sure that the chip can actually be clocked at that low a rate,
and I'd
choose a larger decimation factor, for example, x40, to give a
master-clock rate
of:

20.480Msps

> 2/ I am not too happy about changing a clock where I try to set a
> filter. What could be the proper argument to the UHD USRP block to set
> the receiver bandwidth to a sub-5 MHz value ?
>
Just set the RX bandwidth in the UHD source block to a sub-5MHz value.
If you're only looking at 512ksps, there may be no discernible
difference between what UHD chooses by default, and when you set it
manually.

You might also want to experiment with different RF Gain settings, to
prevent mixing products from forming early in the RF chain, before the
IF filter has a chance to do its thing.




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