[Discuss-gnuradio] Tx and Rx delay within USRP motherboard and daughterboard

Hi,

I did a test to figure out how much delay is within the hardware (FPGA DUC/DDC, ADC/DAC, mixer, filters and amplifiers, etc.)

In the test using UHD at host side, signal transmission is scheduled at t0 and received at t0 + T. The receiving synchronization is based on cross-correlation which should be quite precise with error below one sample.

I set my X310 + SBX at sampling rate of 15.36MS/s and 30.72MS/s and measured the delay T as about 3.1us and 1.6us respectively. It seems to be scaling linearly down versus sampling rate.

The loop-back test can only measure the total TX+RX delay. However, it'd be more interesting to know:

- what are the TX and RX delays specifically

- what is the major part of in the delay (filters in the FPGA?)

Thanks.

Br, Hanwen