Hi Bowen,
I don't spend a lot of time on this ML but I'm very interested in this project as I could make heavy use of it in the future. I currently work on VHDL support in Verilator and I know that handling HDL (Verilog/SystemVerilog/VHDL) is quite hard.
Using regex is a good idea although it's super fragile as you cannot expect the output to be always as you think.
I see two other scenarios for your issue :
1) Don't use regex at all.
Force the the port names and use a defined interface like AXI4 stream (one for input and one for output) (which a standard in HDL design (http://www.mrc.uidaho.edu/mrc/people/jff/EO_440/Handouts/AMBA%20Protocols/AXI-Stream/IHI0051A_amba4_axi4_stream_v1_0_protocol_spec.pdf).
Then let the user wrap it in a new toplevel that matches your interface port names.
As a future enhancement you could like 'autodetect' the port names.
2) Reuse the tools like Verilator to dump the port names.
I personally would go for (1) as it's easy to implement and does all the stuff to have a functional project from my point of view.
Feel free to contact me if I can help you.
Sébastien
Le sam. 22 juin 2019 à 10:32, Derek Kozel <derek@bitstovolts.com> a écrit :
_______________________________________________Hi Bowen,Unless there is a strong reason not to use the STL regex, it is better not to add a new dependency. You can currently developing with GnU Radio 3.7 which does not require C++11, but the next release, 3.8, does require it, so I'd recommendation using the STL version and make C++11 required for your OOT module already.On Sat, Jun 22, 2019, at 5:53 AM, Bowen Hu wrote:Hi all,I am working on the gr-verilog bock which make the Verilog module work with GNU Radio at real-time. As a part of function of this block, I need to parse the source code that Verilator , a tool that convert Verilog code into C++, generated.I am implementing this feature with regex. But I am not sure which tool should I use in GNU Radio, C++11 STL Regex or Boost.Regex?Thank you, if you could give me some advice.Best regards,
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