Friday, June 21, 2019

[Discuss-gnuradio] Fw: [GSoC19] Weekly report of Verilog simulation phase 1 week 3

Hi all,

This is my weekly report last week, I do not why it did not show up in the mail list, so I send it again.

I apologize for the trouble caused by this.

Best regards,​
Bowen​



From: Bowen Hu
Sent: Monday, June 17, 2019 13:07
To: discuss-gnuradio@gnu.org
Subject: [GSoC19] Weekly report of Verilog simulation phase 1 week 3
 
Hi all,

The following content is the abstract  of report, please find the full report at the link above.​
​​
##Progress this week​
I was working on my final exam this week, so I did not do much actual work. But I post a report about the implementation of the Verilog_data class, you can find it here(https://b0wen-hu.github.io/2019/06/16/Implementation-of-Verilog_data/).​

##Plan next week​
I will work on the parse function next week, but I plan to move the function from Verilog_data to the block class.​
##Issue(s)​
Though my final exam is not over yet, I will more time in the next week.​
Best regards,​
Bowen​

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