GSoC 2025 FM Receiver App — A PyQt5-based FM Receiver with GNU Radio Integrated

Hi everyone,

For the past 14 weeks, I've been developing a PyQt5-based FM Broadcast Receiver App with the help of my mentors and this awesome community.

I've finally wrapped up my GSoC 2025 project with RDS support, station scanning, and multi-recording built on GNU Radio.

Blog summary: https://studhamza.github.io/hamza-folio/blog/2025/gnu-week14_final/
Source code & docs: GitHub Page

Would love feedback or suggestions!

Really had fun interacting and learning from everyone; and hopefully I would stick around. Thank you all.

Best,
Hamza

Seeking Consultants for DVB-S/S2(X) and LoRa SDR Projects

Hello,

I'm Dr. Moses Browne Mwakyanjala, CEO of Remos Space Systems AB, a European aerospace company specializing in software-defined ground station solutions for small satellite operators. Our offerings include high-performance software modems, advanced mission control systems, and turnkey ground station deployments. We've proudly delivered solutions to several national space agencies worldwide.

We are currently seeking experienced consultants for two specialized SDR projects:
1. DVB-S/S2(X) Development in C++
• Implement DVB-S/S2(X) modulation/demodulation in C++.
• Optimize for performance with modern SDR platforms.
• Strong understanding of standards compliance, FEC, and advanced signal processing is essential.
2. LoRa SDR Development
• Implement the LoRa PHY layer for SDR platforms.
• LoRaWAN integration experience is a plus.
• Focus on flexible, software-defined deployments.

These are contract roles with flexible, remote collaboration, working closely with our in-house engineering team.

If you're interested, please send your CV, relevant project portfolio, and availability to mbkitine@gmail.com. Recommendations and referrals are also welcome.

Kind regards,
Moses

Dr Moses Browne Mwakyanjala

Founder - CEO

Remos Space Systems AB

m: +46 (0)70 278 2174

a: Aurorum 1C,  977 75 Luleå, Sweden

w: www.remosspace.com e: mbkitine@gmail.com 

GRCon25 - Less Than One Week to Register at Regular Prices

Join Us at GRCon25 - 8-12 September, Everett WA!

The 15th annual GNU Radio Conference (GRCon25) will take place 8-12 September 2025 at the Edward Hansen Conference Center in Everett, Washington, in the greater Seattle area. GRCon is the premier event for the Free and Open Source Software Radio community, bringing together developers, researchers, industry leaders, and hobbyists from around the world.

Full conference details are available at gnuradio.org/grcon25.

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Registration Deadline Approaching

Regular-price registration ends Friday, August 15. After that date, prices increase.

All attendees registered by August 15 will be entered into a drawing to win a HydraSDR RFOne - delivering laboratory-grade performance with 24 MHz to 1.8 GHz coverage, 12-bit ADC resolution, and GNU Radio integration.

Thanks to HydraSDR for sponsoring this giveaway - even more will be given away throughout the week.

Register now at tickets.gnuradio.org.

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Main Track Sessions

Our main track sessions will include presentations from both new and returning contributors, offering insights into the latest developments in wireless communications, signal processing, and SDR hardware and applications.

We are also pleased to announce our keynote speakers:

• Prof. Joshua R. Smith - Milton and Delia Zeutschel Professor at the University of Washington (Allen School of Computer Science & ECE), Director of the UW+Amazon Science Hub, and global leader in sensor systems, wireless power, and ubiquitous computing. IEEE and National Academy of Inventors Fellow.
  

• Dr. Tom Rondeau - Principal Director for the FutureG Office, U.S. Department of Defense, and former DARPA Program Manager. Former lead of the GNU Radio project, with a career spanning open source SDR, national security, and advanced wireless research.
  

• Bradley M. Kuhn - Policy Fellow and Hacker-in-Residence at Software Freedom Conservancy. Former FSF Executive Director, creator of the Affero GPL, and lifelong advocate for software freedom, GPL enforcement, and FOSS community infrastructure.
  

• Jesse Alexander (WB2IFS) - Senior member of IEEE, Radio Club of America, and ARRL, with over 40 years of experience in STEM education, knowledge management, wireless systems, and amateur radio leadership.
  
  

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Workshops - In Person Only

GRCon25 features a wide range of workshops available exclusively to in-person attendees.

Monday kicks off with New User-focused content and a special invited workshop:

Paul Clark - Tutorials from his new No Starch Press book Practical SDR, introducing hobbyists, students, and engineers to practical SDR concepts.

We also have Dan Boschen returning to present a new invited workshop: Quantifying Signal Quality: Practical Tools for High-Fidelity Waveform Analysis.

Additional workshops throughout the week include:

• Communications Basics - Wylie Standage-Beier
  

• Reverse Engineering a Simple Remote - Dr. Neil Rogers
  

• GNU Radio on Embedded SDRs - Philip Balister, Toby Flynn
  

• Simple Replay Attack Demo with GNU Radio - Murat Sever
  

• GR4 Block Design Tutorial - Josh Morman
  

• You Can Do Everything with MultiUSRP, and for Everything Else There is RFNoC - Marian Koop (NI)
  

• GPU Accelerated Block Development - John Sallay
  

• USRP FPGA Processing Using RFNoC - Neel Pandeya
  
  

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Amateur Radio Exams

Amateur Radio license exams will be offered on Thursday, September 11. Please indicate during registration if you plan to take the exam. The exam itself is free, but a nominal FCC fee must be paid prior to taking it. See larc-vec.org/licensing.php for details.

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Capture the Flag

GRCon25 will host its popular Capture the Flag competition, with prizes and bragging rights for the winners. A dedicated conference room will be available for participants to collaborate and work on the challenges throughout the event.

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Evening Events

• Monday Evening - Meet and Greet Reception for all attendees following the first day's workshops.
  

• Wednesday Evening - Social Event sponsored by NI/Emerson, celebrating 20 years of the USRP!
  
  

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Sponsors and Expo Hall

Our generous sponsors make GRCon25 possible. Most will be showcasing their products and demos in the expo hall throughout the week. See the full list at Our Sponsors.

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Related Event - ZRDC 2025

The weekend following GRCon25, the Zero Retries Digital Conference (ZRDC) will be held at the same venue. This independently organized event focuses on technological innovation in amateur radio, featuring presentations and demonstrations on topics such as:

• The IP400 Networking Project
  

• M17 Digital Voice/Data System (with repeater demonstrations)
  

• MMDVM-TNC data system (with repeater demonstrations)
  

• AREDN, HamWAN, and other microwave networking
  

Details at zeroretries.org/p/conference.

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Register today to secure your spot at GRCon25 and join the world's leading open source SDR community in Everett this September.

Register Now

Box 'o radios

I have qty 110 of the older RTL-SDR radios that I want to liquidate. 
These are from before Nooelec and RTL-SDR.com really got into this game,
but all should work.

Various types and RF connectors.

I'm asking U$800.00 for the lot, not including shipping.

Im I making a fundamental mistake?

Dear GNURADIO friends,

I'm wondering if I am making a fundamental mistake or an implementation mistake.

You don't have to debug; thanks for sharing your thoughts! 

Summarized: The RTL-SDR has an 28.8MHz oscillator and I'm feeding this clock-signal into a fractional divider which brings it to a 500Hz audio tone. Please notice this process is carried out with hardware components and is not affected by computer interrupts etc.

The 500Hz audio signal is fed into a regular HAM FM 145MHz transmitter.

The signal is received by an RTL-SDR USB and goes in a SOAPY GNURADIO source block and is decimated to 256000 sampless and demodulated resulting into 500Hz audio tone.
I assume(!) that the IQ sample rate is defined by the SDR receiver and deducted from its 28.8Mhz clock.  
I calculated that with an sample rate of 256K it takes 512 samples =(1500)(1256000)  to cover the cycle time of a 500Hz sine wave.
In a GNURADIO C++ OOT block (based on the very useful GR OOT Cpp tutorial) I re-create (based on the incoming a IQ-stream) with a  sample counter in combination with a look-up table a synthetic sine wave of 500Hz.
I expect that the demodulated 500Hz FM signal  and created synthetic 500Hz signal have exactly the same frequency but I am facing a phase drift between them…
Both 500Hz signals though origin from the same source (the 28.8MHz) SDR clock which defines the audio tone and the sample rate.
I'm wondering if I (still a beginner) am making a fundamental digital signal processing mistake or simply making an implementation mistake which I have to deep dive further into.
After several months I am still learning but got stuck and highly appreciate if you share your thoughts.
My question: Is this approach theoretically possilbe?
Thanks,
Robert PA0BRT

files fyi: Recorded IQ, 2Ch_audio, GRC, Video, OOT_Cpp, lookup_table_synthetic_sine
https://tinyurl.com/3pryf9kb

Re: Adding a Clock IP to RFNoC Block

Hey Jons,

I responded on the usrp-users list (didn't see that you had cross-posted).

--M

On Sat, Jul 26, 2025 at 10:18 AM Jons <jonsdeburn@gmail.com> wrote:

Hi all,

I am trying to add a custom RFNoC block and my block runs on different clocks(not the default ones). So I followed the instructions from the FAQ page in RFNoC wiki of deriving clocks from the available clocks - https://kb.ettus.com/RFNoC_Frequently_Asked_Questions#How_do_I_add_a_clock_with_a_different_frequency.3F But when I add the parameters in block YAML, it added new ports to my rfnoc_block_myblock module, which is not what I expected. My intention was to derive 2 clocks from the rfnoc_chdr_clk  and use it inside my block. For this I added the clock IP module (instantiated) in the noc_shell_myblock, because this is where the CDC FIFOs are there. So, with this method the generated clock just stays inside my block and won't be available outside to it. Maybe the steps described in the FAQ might not be the right way to go about with my requirement? I am not sure.

Also, I tried not adding the YAML parameters of the clocks for my block. This worked to the point where the implementation of the entire design failed with WNS of -0.8ns on the new derived clock I added. I also got a few Critical warnings for the clocks I added, not sure if it is related somehow or if I can ignore it -

TIMING-4#1 Critical Warning
Invalid primary clock redefinition on a clock tree  
Invalid clock redefinition on a clock tree. The primary clock x4xx_core_i/rfnoc_image_core_i/b_myblock_3/noc_shell_myblock_i/clk_wiz_chdr_200_125_inst/inst/clk_in_chdr is defined downstream of clock clk200 and overrides its insertion delay and/or waveform definition.

I followed this thread (https://www.mail-archive.com/usrp-users%40lists.ettus.com/msg14663.html) to add IPs of my clock module that I generated with with Vivado IP catalog and copied the .xci, .v and other generated files into the path/to/module/rfnoc/fpga/myblock/ip/ and changed the Makefile and block YAML definitions like the example given in the example Gain block.

Any tips or leads in adding custom derived clocks to the design would be super helpful and thank you all for maintaining such a nice community!!

-J

Adding a Clock IP to RFNoC Block

Hi all,

I am trying to add a custom RFNoC block and my block runs on different clocks(not the default ones). So I followed the instructions from the FAQ page in RFNoC wiki of deriving clocks from the available clocks - https://kb.ettus.com/RFNoC_Frequently_Asked_Questions#How_do_I_add_a_clock_with_a_different_frequency.3F But when I add the parameters in block YAML, it added new ports to my rfnoc_block_myblock module, which is not what I expected. My intention was to derive 2 clocks from the rfnoc_chdr_clk  and use it inside my block. For this I added the clock IP module (instantiated) in the noc_shell_myblock, because this is where the CDC FIFOs are there. So, with this method the generated clock just stays inside my block and won't be available outside to it. Maybe the steps described in the FAQ might not be the right way to go about with my requirement? I am not sure.

Also, I tried not adding the YAML parameters of the clocks for my block. This worked to the point where the implementation of the entire design failed with WNS of -0.8ns on the new derived clock I added. I also got a few Critical warnings for the clocks I added, not sure if it is related somehow or if I can ignore it -

TIMING-4#1 Critical Warning
Invalid primary clock redefinition on a clock tree  
Invalid clock redefinition on a clock tree. The primary clock x4xx_core_i/rfnoc_image_core_i/b_myblock_3/noc_shell_myblock_i/clk_wiz_chdr_200_125_inst/inst/clk_in_chdr is defined downstream of clock clk200 and overrides its insertion delay and/or waveform definition.

I followed this thread (https://www.mail-archive.com/usrp-users%40lists.ettus.com/msg14663.html) to add IPs of my clock module that I generated with with Vivado IP catalog and copied the .xci, .v and other generated files into the path/to/module/rfnoc/fpga/myblock/ip/ and changed the Makefile and block YAML definitions like the example given in the example Gain block.

Any tips or leads in adding custom derived clocks to the design would be super helpful and thank you all for maintaining such a nice community!!

-J