[Discuss-gnuradio] Using FPGA registers with custom Verilog code

I am running a custom feedback controller on the USRP1. So far I have been content with hard coding parameters of the controller and re-synthesizing the Verilog as needed. However I would like to explore using the FPGA registers to set some parameter values using the python function _write_fpga_reg(....).

What is the best way to go about setting up the Verilog to do this? After looking at the usrp_std.v top level module, I included and setup the serial_io and io_pins modules in my code and then used setting_reg to read the register values. When I do this, the code synthesizes fine but does not produce any output. Are there other modules that serial_io and io_pins depend on? Or am I going about this the wrong way?

Thanks!

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